MC68HC908JW32_09 Datasheet, PDF (109/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Functional Description
Addr.
Register Name
Timer 1 Status and Control ^Read:
$000A
Register Write:
(T1SC) Reset:
Timer 1 Counter ^Read:
$000C
Register High Write:
(T1CNTH) Reset:
Timer 1 Counter ^Read:
$000D
Register Low Write:
(T1CNTL) Reset:
Timer 1 Counter Modulo ^Read:
$000E
Register High Write:
(T1MODH) Reset:
Timer 1 Counter Modulo ^Read:
$000F
Register Low Write:
(T1MODL) Reset:
Read:
$0010
Timer 1 Channel 0 Status and
Control Register (T1SC0)
Write:
Reset:
Timer 1 Channel 0 ^Read:
$0011
Register High Write:
(T1CH0H) Reset:
Timer 1 Channel 0 ^Read:
$0012
Register Low Write:
(T1CH0L) Reset:
Read:
$0013
Timer 1 Channel 1 Status and
Control Register (T1SC1)
Write:
Reset:
Timer 1 Channel 1 ^Read:
$0014
Register High Write:
(T1CH1H) Reset:
Timer 1 Channel 1 ^Read:
$0015
Register Low Write:
(T1CH1L) Reset:
Bit 7
TOF
0
0
Bit 15
0
Bit 7
0
Bit 15
1
Bit 7
1
CH0F
0
0
Bit 15
Bit 7
CH1F
0
0
Bit 15
Bit 7
6
5
4
3
2
TOIE
TSTOP
0
TRST
0
PS2
0
1
0
0
0
14
13
12
11
10
0
0
0
0
0
6
5
4
3
2
0
14
1
6
1
CH0IE
0
14
0
13
1
5
1
MS0B
0
13
6
5
CH1IE
0
0
0
14
13
6
5
= Unimplemented
0
0
12
11
1
1
4
3
1
1
MS0A ELS0B
0
0
12
11
Indeterminate after reset
4
3
Indeterminate after reset
MS1A ELS1B
0
0
12
11
Indeterminate after reset
4
3
Indeterminate after reset
0
10
1
2
1
ELS0A
0
10
2
ELS1A
0
10
2
Figure 8-2. TIM I/O Register Summary
1
Bit 0
PS1
PS0
0
0
9
Bit 8
0
0
1
Bit 0
0
9
1
1
1
TOV0
0
9
0
Bit 8
1
Bit 0
1
CH0MAX
0
Bit 8
1
Bit 0
TOV1
0
9
CH1MAX
0
Bit 8
1
Bit 0
8.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the TIM clock pin, TCLK. The
prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in
the TIM status and control register select the TIM clock source.
8.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
109