MC68HC908JW32_09 Datasheet, PDF (43/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Configuration Register 2 (CONFIG2)
STOP — STOP Instruction Enable
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Chapter 16 Computer Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
3.4 Configuration Register 2 (CONFIG2)
Address:
Read:
Write:
Reset:
$001D
Bit 7
6
5
4
3
2
1
STOP_ STOP_RC
XCLKEN CLKEN
R
VREG33D
0
0
0
0
0
0
0
= Unimplemented
†† Reset by POR only.
Figure 3-3. Configuration Register 2 (CONFIG2)
Bit 0
URSTD
0
STOP_XCLKEN — Crystal Oscillator Stop Mode Enable
Setting STOP_XCLKEN enables the external crystal (XTAL) oscillator to continue operating during
stop mode, in the other words, SIMOSCEN hold high during STOP mode. When this bit is cleared, the
external XTAL oscillator will be disabled during stop mode. Reset clears this bit.
1 = XTAL oscillator enabled during stop mode
0 = XTAL oscillator disabled during stop mode
STOP_RCCLKEN — RC clock Stop Mode Enable
Setting STOP_RCCLKEN enables the internal RC clock to continue operating during STOP mode.
When this bit is cleared, the internal RC clock will be disabled during STOP mode. Reset clears this bit.
1 = Internal RC clock enabled during stop mode
0 = Internal RC clock disable during stop mode
VREG33D — 3.3V USB Regulator Disable Bit
VREG33D disables the USB 3.3V regulator completely.
1 = VREG33 regulator is disabled
0 = VREG33 regulator is enabled
URSTD — USB Reset Disable Bit
URSTD disables the USB reset signal generating an internal reset to the CPU and internal registers.
Instead, it will generate an interrupt request to CPU.
1 = USB reset generates a interrupt request to CPU
0 = USB reset generates a chip reset
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
43