MC68HC908JW32_09 Datasheet, PDF (57/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Chapter 5
Clock Generator Module (CGM)
5.1 Introduction
This section describes the clock generator module (CGM). The CGM generates the base clock signal,
CGMOUT, which is based on either the oscillator clock divided by two or the divided phase-locked loop
(PLL) clock, CGMVCLK, divided by three. CGMOUT is the clock from which the SIM derives the system
clocks, including the bus clock, which is at a frequency of CGMOUT 2.
The PLL is a frequency generator designed for use with a crystal (4MHz) to generate a base frequency
and dividing to a maximum bus frequency of 8MHz.
5.2 Features
Features of the CGM include:
• Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal
reference
• Low-frequency crystal operation with low-power operation and high-output frequency resolution
• Programmable prescaler for power-of-two increases in frequency
• Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• CPU interrupt on entry or exit from locked condition
• Configuration register bit to allow oscillator operation during stop mode
5.3 Functional Description
The CGM consists of three major sub-modules:
• Oscillator module — The oscillator module generates the constant reference frequency clock,
CGMRCLK (buffered CGMXCLK).
• Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock,
CGMVCLK.
• Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by
two or the divided VCO clock, CGMVCLK, divided by three as the base clock, CGMOUT. The SIM
derives the system clocks from either CGMOUT or CGMXCLK.
Figure 5-1 shows the structure of the CGM.
Figure 5-2 is a summary of the CGM registers.
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
57