MC68HC908JW32_09 Datasheet, PDF (187/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

IRQ Pin
Addr.
$001C
$001E
Register Name
Bit 7
IRQ Option Control Register ^{Read: 0}
(IOCR) _Write:
Reset: 0
IRQ Status and Control Register ^{Read: 0}
(ISCR) _Write:
Reset: 0
6
5
0
0
0
0
0
0
0
0
= Unimplemented
4
3
2
1
Bit 0
0
0
PTE3IF
PTE3IE IRQPD
0
0
0
0
0
0
IRQF
0
IMASK MODE
ACK
0
0
0
0
0
Figure 14-2. IRQ I/O Register Summary
14.4 IRQ Pin
The IRQ pin has a low leakage for input voltages ranging from 0V to V_DD; suitable for applications using
RC discharge circuitry to wake up the MCU.
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear,
or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set,
both of the following actions must occur to clear IRQ:
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK
bit in the interrupt status and control register (ISCR). The ACK bit is useful in applications that poll
the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an
interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not
affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit
latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program
counter with the vector address at locations $FFF8 and $FFF9.
• Return of the IRQ pin to logic one — As long as the IRQ pin is at logic zero, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to logic one may occur in any order. The
interrupt request remains pending as long as the IRQ pin is at logic zero. A reset will clear the latch and
the MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or
software clear immediately clears the IRQ latch.
The IRQF bit in the ISCR register can be used to check for pending interrupts. The IRQF bit is not affected
by the IMASK bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
NOTE
An internal pullup resistor to V_DD is connected to IRQ pin; this can be
disabled by setting the IRQPD bit in the IRQ option control register
($001C).
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
187