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| MC68HC908JW32_09 Datasheet, PDF (203/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers | |||
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LVI Status Register
17.4 LVI Status Register
The LVI status register (LVISR) indicates if the VDD voltage was detected below VTRIPF1.
Address:
Read:
Write:
Reset:
$FE0F
Bit 7
LVIOUT
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 17-3. LVI Status Register
1
Bit 0
0
0
0
0
LVIOUT â LVI Output Bit
This read-only flag becomes set when the VDD or VREG falls below their respective trip voltages. Reset
clears the LVIOUT bit.
Table 17-1. LVIOUT Bit Indication
VDD, VREG
VDD > VTRIPR1
VDD < VTRIPF1
VTRIPF1 < VDD < VTRIPR1
LVIOUT
0
1
Previous value
17.5 LVI Interrupts
The LVI module does not generate interrupt requests.
17.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
17.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
17.6.2 Stop Mode
If enabled in stop mode (LVISTOP = 1), the LVI module remains active in stop mode. If enabled to
generate resets (LVIRSTD = 0), the LVI module can generate a reset and bring the MCU out of stop
mode.
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
203
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