MC68HC908JW32_09 Datasheet, PDF (64/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Clock Generator Module (CGM)
9. Program the PLL registers accordingly:
a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P.
b. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E.
c. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high
(PMSH), program the binary equivalent of N.
d. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L.
e. In the PLL reference divider select register (PMDS), program the binary coded equivalent
of R.
NOTE
The values for P, E, N, L, and R can only be programmed when the PLL is
off (PLLON = 0).
Table 5-1 provides numeric examples (numbers are in hexadecimal notation):
Table 5-1. Numeric Examples
CGMVCLK
48 MHz
48 MHz
CGMPCLK
24 MHz
24 MHz
f_BUS
8 MHz
8 MHz
f_RCLK
4 MHz
4 MHz
R N PE L
1 0C 0 2 60
1 06 1 2 60
5.3.7 Special Programming Exceptions
The programming method described in 5.3.6 Programming the PLL does not account for three possible
exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for
these exceptions:
• A 0 value for R or N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the source for the base clock.
See 5.3.8 Base Clock Selector Circuit.
5.3.8 Base Clock Selector Circuit
This circuit is used to select either the oscillator clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The CGMXCLK clock is divided by two while the CGMVCLK is
divided by three to correct the duty cycle. The two divided clocks go through a transition control circuit
that to change from one clock source to the other. During this time, CGMOUT is held in stasis. Therefore,
the bus clock frequency, which is one-half of the base clock frequency, is either one-fourth the frequency
of the selected clock (CGMXCLK) or one-sixth the frequency of the selected CGMVCLK clock.
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The divided VCO
clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned
off if the divided VCO clock is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the divided VCO clock. The divided VCO clock also cannot be selected as the
base clock source if the factor L is programmed to a 0. This value would set up a condition inconsistent
with the operation of the PLL, so that the PLL would be disabled and the oscillator clock would be forced
as the source of the base clock.
MC68HC908JW32 Data Sheet, Rev. 6
64
Freescale Semiconductor