MC68HC908JW32_09 Datasheet, PDF (102/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Monitor Mode (MON)
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security
bytes on pin PTA0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all ROM locations and execute code from ROM. Security remains bypassed
until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and
security code entry is not required. (See Figure 7-7.)
V_DD
RST
4096 + 32 CGMXCLK CYCLES
256 BUS CYCLES (MINIMUM)
PTA0
FROM HOST
FROM MCU
1
4
1
1
2
4
1
NOTES:
1 = Echo delay, approximately 2 bit times.
2 = Data return delay, approximately 2 bit times.
4 = Wait 1 bit time before sending next byte.
Figure 7-7. Monitor Mode Entry Timing
Upon power-on reset, if the received bytes of the security code do not match the data at locations
$FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but
reading a ROM location returns an invalid value and trying to execute code from ROM causes an illegal
address reset. After receiving the eight security bytes from the host, the MCU transmits a break character,
signifying that it is ready to receive a command.
NOTE
The MCU does not transmit a break character until after the host sends the
eight security bits.
To determine whether the security code entered is correct, check to see if bit 6 of RAM address $60 is
set. If it is, then the correct security code has been entered and ROM can be accessed.
MC68HC908JW32 Data Sheet, Rev. 6
102
Freescale Semiconductor