MC68HC908JW32_09 Datasheet, PDF (156/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

USB 2.0 FS Module
11.5.2 USB Status Register (USBSR)
Address: $0052
Bit 7
6
5
4
3
2
1
Bit 0
Read: CONFIG
Write:
SETUP
SOF
CONFIG_
CHG
USBRST
RESUMEF SUSPND
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-4. USB Status Register
CONFIG — Configuration Number
This read-only bit specify the configuration number returned from the USB host. The module only
supports a single configuration setting.
1 = Device configure to configuration number 1
0 = Device is unconfigured
SETUP — SETUP Request Received
This read/write bit indicates a valid GET_DESCRIPTOR command, SYNC_FRAME command or
class/vendor specific request is detected. This bit only set when the packet is received without
CRC/Token/EOP error. When this is set, user must read and decode the request from the endpoint 0
data registers (UE0D7-0). Writing zero to clear the bit. Writing one to the bit has no effect. Reset clears
this bit.
1 = GET_DESCRIPTOR, SYNC_FRAME or Class/vendor specific requests received
0 = No vendor specific request received
SOF — Start of Frame Detection Flag
This read/write bit indicates a start-of-frame signal is detected from the USB data line. Writing zero to
clear the bit. Writing one to the bit has no effect. Reset clears this bit.
1 = Start-of-frame is detected
0 = No start-of-frame is detected
CONFIG_CHG — Change of Configuration Detection Flag
This read/write bit indicates a change of device configuration request is received from the host. This
bit will be set when new configuration is requested and accepted by the host. Writing zero to clear the
bit. Writing one to the bit has no effect. Reset clears this bit.
1 = A change of configuration request is received
0 = No change of configuration request is received
USBRST — USB Reset Detection Flag
This read/write bit is set when a valid reset signal state is detected on the D+ and D- lines. If URSTD
bit of the configuration register (CONFIG) is clear, this reset detection flag will generate a MCU internal
reset signal to reset the CPU and its peripheral. Otherwise, if URSTD is set, a interrupt request will be
generated instead. Writing zero to clear the bit. Writing one to the bit has no effect. Reset clears this bit.
1 = USB reset signal is detected
0 = No USB reset signal is detected
RESUMEF — RESUME Detection Flag
This read/write bit is set when bus activity is detected while the device is in SUSPEND mode. Writing
zero to clear the bit. Writing one to the bit has no effect. Reset clears this bit.
1 = USB bus activity is detected while the device is in SUSPEND mode
0 = No USB bus activity is detected
MC68HC908JW32 Data Sheet, Rev. 6
156
Freescale Semiconductor