MC68HC908JW32_09 Datasheet, PDF (158/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

USB 2.0 FS Module
USBRSTIE — USB RESET Interrupt Mask
This read/write bit enables a CPU interrupt request when USBRST flag of USB status register
(USBSR) and URSTD bit of configuration register (CONFIG) is set. Reset clears this bit.
1 = CPU interrupt request is enabled when USB reset signal is detected
0 = CPU interrupt request is disabled when USB reset signal is detected
RESUMEFIE — Resume Interrupt Mask
This read/write bit enables a CPU interrupt request when the USB bus activity is resumed or
RESUMEF of USB status register (USBSR) is set. Reset clears this bit.
1 = CPU interrupt request is enabled when USB bus activity is resumed
0 = CPU interrupt request is disabled when USB bus activity is resumed
SUSPNDIE — Suspend Mode Interrupt Mask
This read/write bit enables a CPU interrupt request when the module entered suspend mode or
SUSPND flag of USB status register (USBSR) is set. Reset clears this bit.
1 = CPU interrupt request is enabled when the module enters suspend mode
0 = CPU interrupt request is disabled when the module enters suspend mode
11.5.4 USB Endpoint 0 Control/Status Register (UEP0CSR)
Address: $0054
Bit 7
6
5
4
3
Read: DSIZE3_OUT DSIZE2_OUT DSIZE1_OUT DSIZE0_OUT
DVALID_IN
Write: DSIZE3_IN DSIZE2_IN DSIZE1_IN DSIZE0_IN
Reset:
0
0
0
0
0
2
1
Bit 0
TFRC_IN DVALID_OUT TFRC_OUT
0
0
0
Figure 11-6. USB Endpoint 0 Control/Status Register
DSIZE[3:0]_OUT — Endpoint 0 Data Size for OUT packet
These bits specify the packet size received for the previous valid OUT packet. The bits are read only.
DSIZE[3:0]_IN — Endpoint 0 Data Size for IN packet
These bits indicates the packet size to be transmitted in response to the next IN packet. The bits are
write only.
DVALID_IN — Data valid enable bit for IN packet
This read/write bit indicates the data in the endpoint buffer is valid and ready to send. Setting this bit
triggers the data transmission. The bit will be cleared automatically by hardware when a successful IN
packet transaction occurred or a valid SETUP packet is received. The bit can also be cleared by writing
zero. When the bit is zero, all IN packets to endpoint zero will be responded by NAK. Reset also clears
this bit.
1 = Data in the EP0 buffer is valid and ready to transmit
0 = Data in the EP0 buffer is not valid
TFRC_IN — Transfer Complete Flag for IN packet
This read/write bit indicates the data in the EP0 buffer is completely transferred to the host. When the
bit is set, all successive IN packet is responded by NAK. Writing zero to clear this bit. Writing one to
the bit has no effect.
1 = Endpoint data transfer completed
0 = Default status
MC68HC908JW32 Data Sheet, Rev. 6
158
Freescale Semiconductor