MC68HC908JW32_09 Datasheet, PDF (81/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

SIM Counter
If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as
an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
6.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources.
6.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V_DD voltage falls to the
LVI_TRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin
(RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK
cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively
pulls down the RST pin for all internal reset sources.
6.3.2.6 Universal Serial Bus (USB) Reset
The USB module will detect a reset signaled on the bus by the presence of an extended SE0 at the USB
data pins of a device. The MCU seeing a single-ended 0 on its USB data inputs for more than 2.5µs treats
that signal as a reset. After the reset is removed, the device will be in the attached, but not yet addressed
or configured, state (refer to Section 9.1 USB Devices of the Universal Serial Bus Specification Rev. 2.0).
The device must be able to accept the device address via a SET_ADDRESS command (refer to Section
9.4 of the Universal Serial Bus Specification Rev. 2.0) no later than 10ms after the reset is removed.
USB reset can be disabled to generate an internal reset. It can be configured to generate IRQ interrupt.
(See Chapter 3 Configuration Registers (CONFIG).)
NOTE
USB reset is disabled when the USB module is disabled by clearing the
USBEN bit of the USB address register (UADDR).
6.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the
clock for the COP module. The SIM counter is 12 bits long.
6.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to
drive the bus clock state machine.
6.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
81