MC68HC908JW32_09 Datasheet, PDF (199/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

COP Control Register
16.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
16.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG).
16.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register
(CONFIG).
Address:
Read:
Write:
Reset:
$001F
Bit 7
6
5
4
3
2
1
COPRS LVISTOP LVIRSTD LVIPWRD
SSREC STOP
0
0
0
0
0
0
0
= Unimplemented
Figure 16-2. Configuration Register (CONFIG)
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
1 = COP timeout period is (8176) × CGMRCLK cycles
0 = COP timeout period is (262,128) × CGMRCLK cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
Bit 0
COPD
0
16.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
Figure 16-3. COP Control Register (COPCTL)
16.5 Interrupts
The COP does not generate CPU interrupt requests.
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
199