MC68HC908JW32_09 Datasheet, PDF (83/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Exception Control
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). (See Figure 6-10.)
FROM RESET
I BBIRTESAEKT?
INTERRUPT?
YES
NO
YES
I-BIT SET?
NO
IRQ1
INTERRUPT?
YES
NO
AS MANY INTERRUPTS
AS EXIST ON CHIP
STACK CPU REGISTERS
SET I-BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
YES
INSTRUCTION?
NO
RTI
YES
INSTRUCTION?
UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 6-10. Interrupt Processing
6.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
83