MC68HC908JW32_09 Datasheet, PDF (90/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

System Integration Module (SIM)
6.7 SIM Registers
The SIM has three memory-mapped registers:
• SIM Break Status Register (SBSR) — $FE00
• SIM Reset Status Register (SRSR) — $FE01
• SIM Break Flag Control Register (SBFCR) — $FE03
6.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop
mode or wait mode. This register is used only in emulation mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
R
R
R
R
R
R
Write:
Note
Reset:
0
Note: Writing a logic 0 clears SBSW.
R
= Reserved
Figure 6-20. SIM Break Status Register (SBSR)
SBSW — Break Wait Bit
SBSW can be read within the break interrupt routine. The user can modify the return address on the
stack by subtracting 1 from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
6.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset provided all previous reset status
bits have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR
bit and clears all other bits in the register.
The register is initialized on power up with the POR bit set and all other bits cleared. During a POR or any
other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32 CGMXCLK
cycles later. If the pin is not above V_IH at this time, then the PIN bit may be set, in addition to whatever
other bits are set.
Address: $FE01
Bit 7
6
5
4
3
2
1
Bit 0
Read: POR
PIN
COP
ILOP
ILAD
USB
LVI
0
Write:
Reset: 1
0
0
0
0
0
0
0
= Unimplemented
Figure 6-21. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
MC68HC908JW32 Data Sheet, Rev. 6
90
Freescale Semiconductor