MC68HC908JW32_09 Datasheet, PDF (206/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Break Module (BRK)
18.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the SIM. The SIM then causes the CPU to load the instruction register with
a software interrupt instruction (SWI) after completion of the current CPU instruction. The program
counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
• Software writes a logic 1 to the BRKA bit in the break status and control register.
When a CPU-generated address matches the contents of the break address registers, the break interrupt
is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and
returns the MCU to normal operation. Figure 18-2 shows the structure of the break module.
IAB15–IAB8
IAB15–IAB0
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
CONTROL
BREAK
IAB7–IAB0
Figure 18-2. Break Module Block Diagram
18.3.1 Flag Protection During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during
the break state.
18.3.2 CPU During Break Interrupts
When the internal address bus matches the value written in the break address registers or when software
writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt timing is:
• When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
• When a break address is placed at an address of an instruction operand, the instruction is
executed before the break interrupt.
• When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction
is executed.
MC68HC908JW32 Data Sheet, Rev. 6
206
Freescale Semiconductor