MC68HC908JW32_09 Datasheet, PDF (214/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Electrical Specifications
Table 19-4. DC Electrical Characteristics (Continued)
Characteristic⁽¹⁾
Symbol
Min
Typ⁽²⁾
Max
Unit
Pullup resistors⁽⁸⁾
PTA0–PTA7 configured as KBI0–KBI7
RST, IRQ, PTD2, PTD3, PTD7
PTE2–PTE3 with USB disabled
PTE2/D+ with USB enabled (to REG33V)⁽⁹⁾
PTE3/D– with USB enabled (to REG33V)⁽¹⁰⁾
PTB0–PTB7 with internal pullup enabled
R_PU1
R_PU2
21
30
39
kΩ
21
30
39
kΩ
R_PU3
4
5
6
kΩ
R_PU4(Idle)
900
—
1575
Ω
R_PU4(Tran)
1425
—
3090
Ω
R_PU5
21
30
39
kΩ
Low-voltage inhibit for external VDD, trip falling voltage
(kick-in)
V_TRIPF1
3.0
3.3
3.5
V
Low-voltage inhibit for external VDD, trip rising voltage
(recovery)
V_TRIPR1
3.07
3.4
3.6
V
1. V_DD = 3.9 to 5.5 Vdc, V_SS = 0 Vdc, T_A = T_L to T_H, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. When V_DD drops below 3.9V, the VREF33 regulator output will not be guaranteed within 3.3V +/- 10%.
4. Run (operating) I_DD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run I_DD.
5. Wait I_DD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on
all outputs. C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait I_DD.
6. If minimum V_DD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V_DD is reached.
7. The internal 2.5V regulator has embedded a LVI_POR circuitry when the regulator voltage drops below V_{LVI_POR_assert}
voltage it triggers the CPU reset. The reset is released when the regulator voltage returns above V_{LVI_POR_release} voltage.
8. R_PU1 and R_PU2 are measured at V_DD = 5.0V
9. The resistor value is measured at V_DD = 3.9 to 5.5 Vdc, V_SS = 0 Vdc.
10. The resistor value is measured at V_DD = 3.9 to 5.5 Vdc, V_SS = 0 Vdc.
19.6 Control Timing
Table 19-5. Control Timing
Characteristic⁽¹⁾
Symbol
Min
Max
Unit
Internal operating frequency⁽²⁾
f_OP
—
8
MHz
RST input pulse width low⁽³⁾
t_RL
100
—
ns
1. V_SS = 0 Vdc; timing shown with respect to 20% V_DD and 70% V_DD, unless otherwise noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
information.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
19.7 Internal RC Clock Timing
Table 19-6. Internal RC Clock Timing
Characteristic⁽¹⁾
Symbol
Min
TYP
Max
Unit
Internal RC Clock frequency
f_OP
74
88
105
kHz
1. V_SS = 0 Vdc; timing shown with respect to 20% V_DD and 70% V_DD, unless otherwise noted.
MC68HC908JW32 Data Sheet, Rev. 6
214
Freescale Semiconductor