MC68HC908JW32_09 Datasheet, PDF (77/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

SIM Bus Clock Control and Generation
Read: IF6
$FE04
Interrupt Status Register 1
(INT1)
Write:
R
Reset: 0
Read: IF14
$FE05
Interrupt Status Register 2
(INT2)
Write:
R
Reset: 0
Read: 0
$FE06
Interrupt Status Register 3
(INT3)
Write:
R
Reset: 0
IF5
IF4
R
R
0
0
IF13
IF12
R
R
0
0
0
0
R
R
0
0
= Unimplemented
IF3
IF2
IF1
R
R
R
0
0
0
IF11
IF10
IF9
R
R
R
0
0
0
0
0
0
R
R
R
0
0
0
R = Reserved
Figure 6-2. SIM I/O Register Summary
0
0
R
R
0
0
IF8
IF7
R
R
0
0
0
IF15
R
R
0
0
6.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 6-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See Chapter 5 Clock Generator Module
(CGM).)
OSC2
OSC1
OSCILLATOR (OSC) MODULE
CGMXCLK
TO TBM
STOP MODE CLOCK
ENABLE SIGNALS
FROM CONFIG2
CGMRCLK
CGMXCLK
SIM COUNTER
SYSTEM INTEGRATION MODULE
PHASE-LOCKED LOOP (PLL)
CGMOUT
÷2
BUS CLOCK
GENERATORS
SIMOSCEN
IT12
TO REST
OF MCU
IT23
TO REST
OF MCU
SIMDIV2
Figure 6-3. CGM Clock Signals
MONITOR MODE
USER MODE
PTC1
6.2.1 Bus Timing
In user mode, the internal bus frequency is either the oscillator output (CGMXCLK) divided by four or the
PLL output (CGMVCLK) divided by six.
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
77