MC68HC908JW32_09 Datasheet, PDF (202/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Low-Voltage Inhibit (LVI)
V_DD
STOP INSTRUCTION
LVISTOP
FROM CONFIG1
LVIPWRD
FROM CONFIG1
LOW V_DD
DETECTOR
V_DD > V_TRIPR1 = 0
V_DD ≤ V_TRIPF1 = 1
FROM CONFIG1
LVIRSTD
LVI RESET
LVIOUT
TO LVISR
Figure 17-2. LVI Module Block Diagram
17.3.1 Low V_DD Detector
The low V_DD detector circuit monitors the V_DD voltage and forces a LVI reset when the V_DD voltage falls
below the trip voltage, V_TRIPF1. The V_DD LVI circuit can be disabled by the setting the LVIPWRD bit in
CONFIG1 register.
17.3.2 Polled LVI Operation
In applications that can operate at V_DD levels below the V_TRIPF1 level, software can monitor V_DD by polling
the LVIOUT bit. In the CONFIG1 register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
17.3.3 Forced Reset Operation
In applications that require V_DD to remain above the V_TRIPF1 level, enabling LVI resets allows the LVI
module to reset the MCU when V_DD falls below the V_TRIPF1 level. In the CONFIG1 register, the LVIPWRD
and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets.
17.3.4 Voltage Hysteresis Protection
Once the LVI has triggered (by having V_DD fall below V_TRIPF1), the LVI will maintain a reset condition until
V_DD rises above the rising trip point voltage, V_TRIPR1. This prevents a condition in which the MCU is
continually entering and exiting reset if V_DD is approximately equal to V_TRIPF1. V_TRIPR1 is greater than
V_TRIPF1 by the hysteresis voltage, V_HYS.
MC68HC908JW32 Data Sheet, Rev. 6
202
Freescale Semiconductor