MC68HC908JW32_09 Datasheet, PDF (40/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Memory
2.5.7 FLASH Block Protect Register
The FLASH block protect register is implemented as an 8-bit I/O register. The value in this register
determines the starting address of the protected range within the FLASH memory.
Address:
Read:
Write:
Reset:
$FE09
Bit 7
6
5
4
3
2
1
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
0
0
0
0
0
0
0
Figure 2-5. FLASH Block Protect Register (FLBPR)
Bit 0
BPR0
0
BPR[7:0] — FLASH Block Protect Bits
BPR[7:1] represent bits [15:9] of a 16-bit memory address. Bits [8:0] are logic 0’s.
Start address of FLASH block protect
16-bit memory address
000000000
BPR[7:1]
BPR0 is used only for BPR[7:0] = $FF, for no block protection.
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block
protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF.
With this mechanism, the protect start address can be X000, X200, etc. (at page boundaries — 512
bytes) within the FLASH memory.
Examples of protect start address:
Table 2-2 FLASH Block Protect Range
BPR[7:0]
Protected Range
$00–$70
The entire FLASH memory is protected.
$70 or $71
(0111 000x)
$7000 to $FFFF
(The entire FLASH memory is protected.)
$72 or $73
(0111 001x)
$7200 to $FFFF
$74 or $75
(0111 010x)
$7400 to $FFFF
and so on...
$EE or $EF
(1110 111x)
$EE00 to $FFFF
$F0 - $FF
The entire FLASH memory is NOT protected.⁽¹⁾
1. The 48-byte user vectors ($FFD0–$FFFF), which are always protected.
MC68HC908JW32 Data Sheet, Rev. 6
40
Freescale Semiconductor