MC68HC908JW32_09 Datasheet, PDF (42/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Configuration Registers (CONFIG)
3.3 Configuration Register 1 (CONFIG1)
Address: $001F
Bit 7
6
5
4
3
Read:
COPRS LVISTOP LVIRSTD LVIPWRD
Write:
Reset: 0
0
0
0
0
= Unimplemented
2
SSREC
0
1
STOP
0
Figure 3-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
COPRS — COP Rate Select
COPRS selects the COP time-out period. Reset clears COPRS. (See Chapter 16 Computer Operating
Properly (COP).)
1 = COP time out period = 8176 CGMRCLK cycles
0 = COP time out period = 262,128 CGMRCLK cycles
LVISTOP — Low Voltage Inhibit Enable in STOP mode bit
When the LVIPWRD bit is clear or the LVIREGD is clear, setting the LVISTOP bit enables the LVI to
operate during STOP mode. Reset clears LVISTOP.
1 = Low voltage inhibit enabled during stop mode
0 = Low voltage inhibit disable during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module.
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module completely. When it is set, LVI trip for V_DD is disabled.
1 = LVI module power and LVI trip for V_DD disabled
0 = LVI module power and LVI trip for V_DD is enabled
SSREC — Short Stop Recovery
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096
CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
NOTE
When the LVISTOP is enabled, the system stabilization time for power on
reset and long stop recovery (both 4096 CGMXCLK cycles) gives a delay
longer than the enable time for the LVI. There is no period where the MCU
is not protected from a low power condition. However, when using the short
stop recovery configuration option, the 32 CGMXCLK delay is less than the
LVI’s turn-on time and there exists a period in start-up where the LVI is not
protecting the MCU.
MC68HC908JW32 Data Sheet, Rev. 6
42
Freescale Semiconductor