MC68HC908JW32_09 Datasheet, PDF (159/232 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

USB Module Registers
DVALID_OUT — Data valid enable bit for OUT packet
This bit indicates valid data is stored in the endpoint buffer, CPU attention is required. User must clear
this bit in order to receive the next OUT packet by writing zero to the bit, otherwise all successive OUT
packet is NAK by the module. Writing one to the bit has no effect. Reset clears this bit.
1 = Data in the EP0 buffer is valid
0 = Data in the EP0 buffer is not valid
TFRC_OUT — Transfer Complete Flag for OUT packet
This read/write bit indicates the a valid OUT or SETUP packet is completely transferred to the EP0
data buffer. When the bit is set, all successive OUT packet will be responded by NAK. Writing zero to
clear this bit. Writing one to the bit has no effect.
1 = Endpoint data transfer completed
0 = Default status
11.5.5 USB Endpoint 1–4 Control Status Register (UEP1CSR–UEP4CSR)
Address: $0055 to $0058
Bit 7
6
5
4
3
2
1
Read:
0
MODE1 MODE0
DIR
SIZE1 SIZE0 DVALID
Write:
STALL
Reset: 0
0
0
0
0
0
0
Figure 11-7. USB Endpoint 1–4 Control Status Register
Bit 0
TFRC
0
TFRC — Transfer Complete Flag
This read/write bit indicates the data transfer associated with the endpoint is completed. When the bit
is set, all successive IN/OUT packet will be responded by NAK. Writing zero to clear this bit. Writing
one to the bit has no effect.
1 = Endpoint data transfer completed
0 = Default status
DVALID — Data valid bit
When the endpoint is configured as IN endpoint, this bit indicates the data in the endpoint buffer is valid
and ready to be sent. Setting this bit arms the data transmission otherwise all IN packets are returned
by NAK. The bit will be cleared automatically by hardware when a successful IN packet transaction
occurred.
When the endpoint is configured as OUT endpoint, this bit indicates valid received data is stored in the
endpoint buffer, CPU attention is required. User must clear this bit in order to receive the next OUT
packet, otherwise all successive OUT packet is responded NAK by the module. Reset clears this bit.
1 = Data in the endpoint buffer is valid
0 = Data in the endpoint buffer is not valid
MC68HC908JW32 Data Sheet, Rev. 6
Freescale Semiconductor
159