EP3C5E144C8N Datasheet, PDF (9/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter Revision Dates
The chapters in this document, Cyclone III Device Handbook, were revised on the
following dates. Where chapters or groups of chapters are available separately, part
numbers are listed.
Chapter 1.
Cyclone III Device Family Overview
Revised:
December 2011
Part Number: CIII51001-2.3
Chapter 2.
Logic Elements and Logic Array Blocks in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51002-2.3
Chapter 3.
Memory Blocks in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51004-2.3
Chapter 4.
Embedded Multipliers in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51005-2.3
Chapter 5.
Clock Networks and PLLs in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51006-4.0
Chapter 6.
I/O Features in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51007-3.3
Chapter 7.
High-Speed Differential Interfaces in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51008-4.0
Chapter 8.
External Memory Interfaces in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51009-3.0
Chapter 9.
Configuration, Design Security, and Remote System Upgrades in the Cyclone III De-
vice Family
Revised:
December 2011
Part Number: CIII51016-2.0
Chapter 10. Hot-Socketing and Power-On Reset in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51011-3.3
Chapter 11. SEU Mitigation in the Cyclone III Device Family
Revised:
December 2011
Part Number: CIII51013-2.3
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1