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10–2
Chapter 10: Hot-Socketing and Power-On Reset in the Cyclone III Device Family
Hot-Socketing Specifications
Devices Driven Before Power-Up
You can drive signals into I/O pins, dedicated input pins, and dedicated clock pins of
Cyclone III device family before or during power-up or power down without
damaging the device. The Cyclone III device family supports any power-up or
power down sequence (V_CCIO, V_CCINT) to simplify system level design.
I/O Pins Remain Tristated During Power-Up
The output buffers of Cyclone III device family are turned off during system
power up or power down. Cyclone III device family does not drive out until the
device is configured and working in recommended operating conditions. The I/O
pins are tristated until the device enters user mode with a weak pull-up resistor (R) to
V_CCIO.
You can power-up or power down the V_CCIO, V_CCA, and V_CCINT pins in any sequence.
The V_CCIO, V_CCA, and V_CCINT pins must have a monotonic rise to their steady state
levels. The maximum power ramp rate is 3 ms for fast POR time and 50 ms for
standard POR time. The minimum power ramp rate is 50 µs. V_CCIO for all I/O banks
must be powered up during device operation. All V_CCA pins must be powered to 2.5 V
(even when PLLs are not used), and must be powered up and powered down at the
same time. V_{CCD_PLL} must always be connected to V_CCINT through a decoupling
capacitor and ferrite bead. During hot-socketing, the I/O pin capacitance is less than
15 pF and the clock pin capacitance is less than 20 pF.
Cyclone III device family meets the following hot-socketing specification:
■ The hot-socketing DC specification is | I_IOPIN | < 300 uA
■ The hot-socketing AC specification is | I_IOPIN | < 8 mA for the ramp rate of 10 ns
or more
For ramp rates faster than 10 ns on I/O pins, |I_IOPIN| is obtained with the equation
I = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate. The
hot-socketing specification takes into account the pin capacitance but not board trace
and external loading capacitance. You must consider additional or separate
capacitance for trace, connector, and loading. I_IOPIN is the current for any user I/O
pins on the device. The DC specification applies when all V_CC supplied to the device is
stable in the powered-up or powered-down conditions.
A possible concern for semiconductor devices in general regarding hot-socketing is
the potential for latch up. Latch up can occur when electrical subsystems are
hot-socketed into an active system. During hot-socketing, the signal pins may be
connected and driven by the active system before the power supply can provide
current to the V_CC of the device and ground planes. This condition can lead to latch up
and cause a low-impedance path from V_CC to ground in the device. As a result, the
device extends a large amount of current, possibly causing electrical damage.
The design of the I/O buffers and hot-socketing circuitry ensures that Cyclone III
device family are immune to latch up during hot-socketing.
f For more information about the hot-socketing specification, refer to the Cyclone III
Device Data Sheet and Cyclone III LS Device Data Sheet chapters and the Hot-Socketing
and Power-Sequencing Feature and Testing for Altera Devices white paper.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation