EP3C5E144C8N Datasheet, PDF (307/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 1: Cyclone III Device Data Sheet
Glossary
1–27
f The Excel-based I/O Timing spreadsheet is downloadable from Cyclone III Devices
Literature website.
Glossary
Table 1–39 lists the glossary for this chapter.
Table 1–39. Glossary (Part 1 of 5)
Letter
Term
A
—
B
—
C
—
D
—
E
—
F
f_HSCLK
GCLK
G
GCLK PLL
H HSIODR
Definitions
—
—
—
—
—
HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.
Input pin directly to Global Clock network.
Input pin to Global Clock network through PLL.
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
Input Waveforms
I
for the SSTL
Differential I/O
VSWING
Standard
V_IH
V_REF
V_IL
TMS
TDI
TCK
J JTAG Waveform
TDO
Signal
to be
Captured
Signal
to be
Driven
K
—
L
—
M
—
t _JCP
t _JCH
t _JCL
t _{JPSU_TDI}
t _{JPSU_TMS}
t _JPH
t_JPZX
t_JSSU
t_JPCO
t _JSH
t_JSZX
t_JSCO
t _JPXZ
t_JSXZ
—
—
—
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 2