EP3C5E144C8N Datasheet, PDF (332/348 Pages) Altera Corporation – Ability to disable external JTAG port

2–18
Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
I/O performance supports several systems interfacing, for example, the high-speed
I/O interface, external memory interface, and PCI/PCI-X bus interface. I/O using
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speed with typical DDR2 SDRAM memory interface setup. I/O using
general purpose I/O standards such as 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are
capable of typical 200 MHz interfacing frequency with 10 pF load.
1 Actual achievable frequency depends on design- and system-specific factors. Perform
HSPICE/IBIS simulations based on your specific design and system setup to
determine the maximum achievable frequency in your system.
High-Speed I/O Specification
Table 2–26 through Table 2–31 list the high-speed I/O timing for Cyclone III LS
devices. For more information about the definitions of high-speed timing
specifications, refer to “Glossary” on page 2–26.
Table 2–26. Cyclone III LS Devices RSDS Transmitter Timing Specification ^{(1), (2)} (Preliminary)
Symbol
Modes
C7 and I7
C8
Unit
Min
Typ
Max
Min
Typ
Max
×10
10
—
155.5
10
—
155.5
MHz
f_HSCLK
(input clock
frequency)
×8
10
—
155.5
10
—
155.5
MHz
×7
10
—
155.5
10
—
155.5
MHz
×4
10
—
155.5
10
—
155.5
MHz
×2
10
—
155.5
10
—
155.5
MHz
×1
10
—
311
10
—
311
MHz
×10
100
—
311
100
—
311
Mbps
×8
80
—
311
80
—
311
Mbps
Device operation
×7
in Mbps
×4
70
—
311
70
40
—
311
40
—
311
Mbps
—
311
Mbps
×2
20
—
311
20
—
311
Mbps
×1
10
—
311
10
—
311
Mbps
t_DUTY
TCCS
—
45
—
55
45
—
55
%
—
—
—
200
—
—
200
ps
Output jitter
(peak to peak)
—
—
—
500
—
—
550
ps
20 – 80%,
t_RISE
—
500
—
—
500
—
ps
C_LOAD = 5 pF
t_FALL
t_LOCK ⁽³⁾
20 – 80%,
—
500
—
—
500
—
ps
C_LOAD = 5 pF
—
—
—
1
—
—
1
ms
Notes to Table 2–26:
(1) Applicable for true RSDS and Emulated RSDS with three-resistor network transmitters.
(2) True RSDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6). Emulated RSDS with three-resistor network
transmitter is supported at the output pin of all I/O banks.
(3) t_LOCK is the time required for the PLL to lock from the end of device configuration.
Cyclone III Device Handbook
Volume 2
December 2011 Altera Corporation