EP3C5E144C8N Datasheet, PDF (342/348 Pages) Altera Corporation – Ability to disable external JTAG port

2–28
Chapter 2: Cyclone III LS Device Data Sheet
Glossary
Table 2–39. Glossary (Part 3 of 6)
Letter
Term
Definitions
The following block diagram highlights the PLL specification parameters.
P PLL Block
CLK
Core Clock
Switchover
CLKOUT Pins
fOUT _EXT
fIN
fINPFD
N
PFD
CP
LF
VCO fVCO
Counters ^fOUT
C0..C4
GCLK
Key
Reconfigurable in User Mode
Phase tap
M
Q
—
R_L
Receiver Input
R ^Waveform
—
Receiver differential input discrete resistor (external to the Cyclone III LS device)
Receiver Input Waveform for LVDS and LVPECL Differential Standards
Single-Ended Waveform
V_ID
V_CM
Positive Channel (p) = V_IH
Negative Channel (n) = V_IL
Ground
Differential Input Waveform
RSKM (Receiver
input skew
margin)
V_ID
0V
V_ID
p-n
High-speed I/O Block: The total margin left after accounting for the sampling window and
TCCS. RSKM = (TUI – SW – TCCS) / 2
Cyclone III Device Handbook
Volume 2
December 2011 Altera Corporation