EP3C5E144C8N Datasheet, PDF (302/348 Pages) Altera Corporation – Ability to disable external JTAG port

1–22
Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications ⁽¹⁾ (Part 2 of 2)
Symbol
Modes
C6
C7, I7
C8, A7
Unit
Min Max Min Max Min Max
Output jitter
(peak to peak)
—
— 500 — 500 — 550 ps
t_LOCK ⁽²⁾
—
—
1
—
1
—
1
ms
Notes to Table 1–30:
(1) Emulated LVDS transmitter is supported at the output pin of all I/O banks.
(2) t_LOCK is the time required for the PLL to lock from the end of device configuration.
Table 1–31. Cyclone III Devices LVDS Receiver Timing Specifications ⁽¹⁾
Symbol
Modes
C6
Min Max
C7, I7
Min Max
C8, A7
Min Max
×10
10 437.5 10 370 10 320
×8
10 437.5 10 370 10 320
f_HSCLK (input
×7
clock frequency)
×4
10 437.5 10 370 10 320
10 437.5 10 370 10 320
×2
10 437.5 10 370 10 320
×1
10 437.5 10 402.5 10 402.5
×10
100 875 100 740 100 640
×8
80 875 80 740 80 640
HSIODR
×7
70 875 70 740 70 640
×4
40 875 40 740 40 640
×2
20 875 20 740 20 640
×1
10 437.5 10 402.5 10 402.5
SW
—
— 400 — 400 — 400
Input jitter
tolerance
—
— 500 — 500 — 550
t_LOCK ⁽²⁾
—
—
1
—
1
—
1
Notes to Table 1–31:
(1) LVDS receiver is supported at all banks.
(2) t_LOCK is the time required for the PLL to lock from the end of device configuration.
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
ps
ps
ms
External Memory Interface Specifications
Cyclone III devices support external memory interfaces up to 200 MHz. The external
memory interfaces for Cyclone III devices are auto-calibrating and easy to implement.
f For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to Literature: External Memory Interfaces.
Cyclone III Device Handbook
Volume 2
December 2011 Altera Corporation