EP3C5E144C8N Datasheet, PDF (89/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
5–29
■ High time count = 2 cycles
■ Low time count = 1 cycle
■ rselodd = 1 effectively equals:
■ High time count = 1.5 cycles
■ Low time count = 1.5 cycles
■ Duty cycle = (1.5/3)% high time count and (1.5/3)% low time count
Scan Chain Description
Cyclone III device family PLLs have a 144-bit scan chain.
Table 5–4 lists the number of bits for each component of the PLL.
Table 5–4. Cyclone III Device Family PLL Reprogramming Bits
Block Name
Counter
Number of Bits
Other
Total
C4 ⁽¹⁾
16
2 ⁽²⁾
18
C3
16
2 ⁽²⁾
18
C2
16
2 ⁽²⁾
18
C1
16
2 ⁽²⁾
18
C0
16
2 ⁽²⁾
18
M
16
2 ⁽²⁾
18
N
16
2 ⁽²⁾
18
Charge Pump
9
0
9
Loop Filter ⁽³⁾
9
0
9
Total number of bits:
144
Notes to Table 5–4:
(1) LSB bit for C4 low-count value is the first bit shifted into the scan chain.
(2) These two control bits include rbypass, for bypassing the counter, and rselodd, to select the output clock duty
cycle.
(3) MSB bit for loop filter is the last bit shifted into the scan chain.
Figure 5–22 shows the scan chain order of the PLL components.
Figure 5–22. PLL Component Scan Chain Order
DATAIN
LF CP
MSB
LSB
N
M
C0
DATAOUT
C4
C3
C2
C1
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1