EP3C5E144C8N Datasheet, PDF (44/348 Pages) Altera Corporation – Ability to disable external JTAG port

3–10
Chapter 3: Memory Blocks in the Cyclone III Device Family
Memory Modes
Table 3–3. Cyclone III Device Family M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)
Read Port
512 × 16
256 × 32
1024 × 9
512 × 18
256 × 36
8192 × 1
v
v
—
—
—
4096 × 2
v
v
—
—
—
2048 × 4
v
v
—
—
—
Write Port
1024 × 8
v
v
—
—
—
512 × 16
v
v
—
—
—
256 × 32
v
v
—
—
—
1024 × 9
—
—
v
v
v
512 × 18
—
—
v
v
v
256 × 36
—
—
v
v
v
In simple dual-port mode, M9K memory blocks support separate wren and rden
signals. You can save power by keeping the rden signal low (inactive) when not
reading. Read-during-write operations to the same address can either output “Don’t
Care” data at that location or output “Old Data”. To choose the desired behavior, set
the Read-During-Write option to either Don’t Care or Old Data in the RAM
MegaWizard Plug-In Manager in the Quartus II software. For more information about
this behavior, refer to “Read-During-Write Operations” on page 3–15.
Figure 3–10 shows the timing waveforms for read and write operations in simple
dual-port mode with unregistered outputs. Registering the outputs of the RAM
simply delays the q output by one clock cycle.
Figure 3–10. Cyclone III Device Family Simple Dual-Port Timing Waveforms
wrclock
wren
wraddress an-1
an
a0
data din-1
din
rdclock
rden
rdaddress
bn
b0
a1
a2
b1
a3
a4
a5
a6
din4
din5
din6
b2
b3
q (asynch) doutn-1
doutn
dout0
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation