EP3C5E144C8N Datasheet, PDF (121/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 6: I/O Features in the Cyclone III Device Family
Document Revision History
6–23
Table 6–7. Document Revision History (Part 2 of 3)
Date
October 2008
May 2008
Version
Changes
■ Added (Note 6) to Table 6–5.
■ Updated the “I/O Banks” section.
■ Updated the “Differential Pad Placement Guidelines” section.
2.1 _{■ Updated the “VREF Pad Placement Guidelines” section.}
■ Removed any mention of “RSDS and PPDS are registered trademarks of National
Semiconductor” from chapter.
■ Updated chapter to new template.
Changes include addition of BLVDS information.
■ Added an introduction to “I/O Element Features” section.
■ Updated “Slew Rate Control” section.
■ Updated “Programmable Delay” section.
■ Updated Table 6–1 with BLVDS information.
■ Updated Table 6–2.
■ Updated “PCI-Clamp Diode” section.
■ Updated “LVDS Transmitter Programmable Pre-Emphasis” section.
■ Updated “On-Chip Termination with Calibration” section and added new Figure 6–9.
■ Updated Table 6–3 title.
■ Updated Table 6–4 unit.
■ Updated “I/O Standards” section and Table 6–5 with BLVDS information and added
2.0
(Note 5).
■ Updated “Differential I/O Standard Termination” section with BLVDS information.
■ Updated “I/O Banks” section.
■ Updated (Note 2) and added (Note 7) and BLVDS information to Figure 6–15.
■ Updated (Note 2) and added BLVDS information to Table 6–6.
■ Added MBGA package information to Table 6–7.
■ Deleted Table 6-8.
■ Updated “High-Speed Differential Interfaces” section with BLVDS information.
■ Updated “Differential Pad Placement Guidelines” section and added new Figure 6–16.
■ Updated “VREF Pad Placement Guidelines” section and added new Figure 6–17.
■ Updated Table 6–11.
■ Added new “DCLK Pad Placement Guidelines” section.
■ Updated “DC Guidelines” section.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1