EP3C5E144C8N Datasheet, PDF (187/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Figure 9–10. Word-Wide Multi-Device AP Configuration
VCCIO (1)
VCCIO (1) ^{VCCIO (1)}
10 k
VCCIO (2)
10 k
10 k
10 k
VCCIO (2)
10 k
CLK
RST#
CE#
OE#
ADV#
WE#
WAIT
DQ[15:0]
A[24:1]
Numonyx P30/P33 Flash
nCE
nCEO
nCE
GND
DCLK
nRESET
FLASH_nCE
nOE
nAVD
nWE
I/O (5)
DATA[15..0]
PADD[23..0]
MSEL[3..0]
(4)
DQ[7..0]
DATA[7..0]
DCLK
nCEO
nCE
MSEL[3..0]
(4)
DQ[7..0]
DATA[7..0]
DCLK
nCEO N.C. (3)
MSEL[3..0] (4)
Cyclone III Master Device
Cyclone III Slave Device
Cyclone III Slave Device
Buffers (6)
VCCIO (1)
10 k
9–29
nCE
nCEO
nCE
nCEO
N.C. (3)
DQ[15..8]
MSEL[3..0] (4)
MSEL[3..0]
(4)
DATA[7..0]
DCLK
DATA[7..0]
DQ[15..8] ^DCLK
Cyclone III Slave Device
Cyclone III Slave Device
Notes to Figure 9–10:
(1) Connect the pull-up resistors to the V_CCIO supply of the bank in which the pin resides.
(2) Connect the pull-up resistor to the V_CCIO supply voltage of the I/O bank in which the nCE pin resides.
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AP mode and the slave
devices in FPP mode. To connect MSEL[3..0] for the master device in AP mode and the slave devices in FPP mode, refer to Table 9–7 on
page 9–11. Connect the MSEL pins directly to V_CCA or GND.
(5) The AP configuration ignores the WAIT signal during configuration mode. However, if you are accessing flash during user mode with user logic,
you can optionally use the normal I/O pin to monitor the WAIT signal from the Numonyx P30 or P33 flash.
(6) Connect the repeater buffers between the Cyclone III master device and slave devices for DATA[15..0] and DCLK. All I/O inputs must maintain a
maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in “Configuration
and JTAG Pin I/O Requirements” on page 9–7.
1 In a multi-device AP configuration, the board trace length between the parallel flash
and the master device must follow the recommendations listed in Table 9–12.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1