EP3C5E144C8N Datasheet, PDF (37/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 3: Memory Blocks in the Cyclone III Device Family
3–3
Overview
Control Signals
The clock-enable control signal controls the clock entering the input and output
registers and the entire M9K memory block. This signal disables the clock so that the
M9K memory block does not see any clock edges and does not perform any
operations.
The rden and wren control signals control the read and write operations for each port
of M9K memory blocks. You can disable the rden or wren signals independently to
save power whenever the operation is not required.
Figure 3–1 shows how the register clock, clear, and control signals are implemented in
the Cyclone III device family M9K memory block.
Figure 3–1. M9K Control Signal Selection
Dedicated
6
Row LAB
Clocks
Local
Interconnect
clock_b
clocken_b
rden_b
wren_b
aclr_b
addressstall_b
byteena_b
clock_a
clocken_a
rden_a
wren_a
aclr_a
addressstall_a
byteena_a
Parity Bit Support
Parity checking for error detection is possible with the parity bit along with internal
logic resources. The Cyclone III device family M9K memory blocks support a parity
bit for each storage byte. You can use this bit as either a parity bit or as an additional
data bit. No parity function is actually performed on this bit.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1