EP3C5E144C8N Datasheet, PDF (337/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
2–23
f For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to Literature: External Memory Interfaces.
Table 2–32. FPGA Sampling Window (SW) Requirement—Read Side ⁽¹⁾ (Preliminary)
Memory Standard
Column I/Os (ps)
Setup
Hold
Row I/Os (ps)
Setup
Hold
Wraparound Mode (ps)
Setup
Hold
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
705
675
900
785
800
1050
765
745
945
C7
650
620
845
C8
720
740
990
I7
710
690
890
770
795
910
930
915
1065
855
880
955
715
740
855
870
855
1005
800
825
900
985
970
1085
1115
1185
1210
1040
1000
1130
930
915
1030
1055
1125
1150
985
945
1075
Note to Table 2–32:
(1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row
I/Os.
Table 2–33. Cyclone III LS Devices Transmitter Channel-to-Channel Skew (TCCS)—Write Side ⁽¹⁾ (Part 1 of 2)
Memory Standard
I/O Standard
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
Column I/Os (ps)
Lead
915
1025
880
1010
910
1010
1040
1180
1010
1160
1040
1190
Lag
C7
410
545
340
380
450
570
C8
440
600
360
410
490
630
Row I/Os (ps)
Lead
Lag
Wraparound Mode (ps)
Lead
Lag
915
410
1015
510
1025
545
1125
645
880
340
980
440
1010
380
1010
480
910
450
1010
550
1010
570
1110
670
1040
440
1140
540
1180
600
1280
700
1010
360
1110
460
1160
410
1260
510
1040
490
1140
590
1190
630
1290
730
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 2