EP3C5E144C8N Datasheet, PDF (106/348 Pages) Altera Corporation – Ability to disable external JTAG port

6–8
Chapter 6: I/O Features in the Cyclone III Device Family
OCT Support
On-Chip Series Termination with Calibration
The Cyclone III device family supports on-chip series termination with calibration in
all banks. The on-chip series termination calibration circuit compares the total
impedance of the output buffer to the external 25-Ω ±1% or 50-Ω ±1% resistors
connected to the RUP and RDN pins, and dynamically adjusts the output buffer
impedance until they match (as shown in Figure 6–2).
The R_S shown in Figure 6–2 is the intrinsic impedance of the transistors that make up
the output buffer.
Figure 6–2. Cyclone III Device Family On-Chip Series Termination with Calibration
Cyclone III Device Family
Driver Series Termination
V_CCIO
Receiving
Device
R_S
Z_O
R_S
GND
OCT with calibration is achieved using the OCT calibration block circuitry. There is
one OCT calibration block in banks 2, 4, 5, and 7. Each calibration block supports each
side of the I/O banks. Because there are two I/O banks sharing the same calibration
block, both banks must have the same V_CCIO if both banks enable OCT calibration. If
two related banks have different V_CCIOs, only the bank in which the calibration block
resides can enable OCT calibration.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation