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EP3C5E144C8N Datasheet, PDF (288/348 Pages) Altera Corporation – Ability to disable external JTAG port | |||
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1â8
Chapter 1: Cyclone III Device Data Sheet
Electrical Characteristics
Example 1â1 shows you the example to calculate the change of 50 Ω I/O impedance
from 25°C at 3.0 V to 85°C at 3.15 V:
Example 1â1.
ÎRV = (3.15 â 3) Ã 1000 Ã â0.026 = â3.83
ÎRT = (85 â 25) Ã 0.262 = 15.72
Because ÎRV is negative,
MFV = 1 / (3.83/100 + 1) = 0.963
Because ÎRT is positive,
MFT = 15.72/100 + 1 = 1.157
MF = 0.963 Ã 1.157 = 1.114
Rfinal = 50 à 1.114 = 55.71 Ω
Pin Capacitance
Table 1â9 lists the pin capacitance for Cyclone III devices.
Table 1â9. Cyclone III Devices Pin Capacitance
Symbol
Parameter
Typical â Typical â
QFP
FBGA
Unit
CIOTB
Input capacitance on top/bottom I/O pins
7
CIOLR
Input capacitance on left/right I/O pins
7
CLVDSLR
Input capacitance on left/right I/O pins with dedicated
LVDS output
8
6
pF
5
pF
7
pF
CVREFLR
(1)
CVREFTB
(1)
CCLKTB
Input capacitance on left/right dual-purpose VREF pin
when used as VREF or user I/O pin
Input capacitance on top/bottom dual-purpose VREF pin
when used as VREF or user I/O pin
Input capacitance on top/bottom dedicated clock input
pins
21
23 (2)
7
21
pF
23 (2)
pF
6
pF
CCLKLR Input capacitance on left/right dedicated clock input pins
6
5
pF
Notes to Table 1â9:
(1) When VREF pin is used as regular input or output, a reduced performance of toggle rate and tCO is expected due to
higher pin capacitance.
(2) CVREFTB for EP3C25 is 30 pF.
Cyclone III Device Handbook
Volume 2
December 2011 Altera Corporation
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