EP3C5E144C8N Datasheet, PDF (322/348 Pages) Altera Corporation – Ability to disable external JTAG port

2–8
Chapter 2: Cyclone III LS Device Data Sheet
Electrical Characteristics
Example 2–1 shows you how to calculate the change of 50 Ω I/O impedance from
25°C at 3.0 V to 85°C at 3.15 V.
Example 2–1.
ΔR_V = (3.15 – 3) × 1000 × –0.026 = –3.83
ΔR_T = (85 – 25) × 0.262 = 15.72
Because ΔR_V is negative,
MF_V = 1 / (3.83/100 + 1) = 0.963
Because ΔR_T is positive,
MF_T = 15.72/100 + 1 = 1.157
MF = 0.963 × 1.157 = 1.114
R_final = 50 × 1.114 = 55.71 Ω
Pin Capacitance
Table 2–9 lists the pin capacitance for Cyclone III LS devices.
Table 2–9. Cyclone III LS Devices Pin Capacitance
Symbol
Parameter
Typical –
QFP
Typical –
FBGA
Unit
C_IOTB
Input capacitance on top/bottom I/O pins
7
C_IOLR
Input capacitance on left/right I/O pins
7
C_LVDSLR
Input capacitance on left/right I/O pins with true LVDS
output
8
6
pF
5
pF
7
pF
C_VREFLR Input capacitance on left/right dual-purpose VREF pin
(1)
when used as V_REF or user I/O pin
21
C_VREFTB Input capacitance on top/bottom dual-purpose VREF
(1)
pin when used as V_REF or user I/O pin
23
C_CLKTB
Input capacitance on top/bottom dedicated clock input
pins
7
21
pF
23
pF
6
pF
C_CLKLR
Input capacitance on left/right dedicated clock input
pins
6
5
pF
Note to Table 2–9:
(1) When you use the VREF pin as a regular input or output, you can expect a reduced performance of toggle rate and
t_CO due to higher pin capacitance.
Cyclone III Device Handbook
Volume 2
December 2011 Altera Corporation