EP3C5E144C8N Datasheet, PDF (73/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Feedback Modes
5–13
No Compensation Mode
In no compensation mode, the PLL does not compensate for any clock networks. This
provides better jitter performance because clock feedback into the PFD does not pass
through as much circuitry. Both the PLL internal and external clock outputs are
phase-shifted with respect to the PLL clock input.
Figure 5–9 shows a waveform example of the phase relationship of the PLL clock in
this mode.
Figure 5–9. Phase Relationship Between PLL Clocks in No Compensation Mode
Phase Aligned
PLL Reference
Clock at the Input Pin
PLL Clock at the
Register Clock Port
(1), (2)
External PLL Clock
Outputs (2)
Notes to Figure 5–9:
(1) Internal clocks fed by the PLL are phase-aligned to each other.
(2) The PLL clock outputs can lead or lag the PLL input clocks.
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin. The external
clock output pin has a phase delay relative to the clock input pin if connected in this
mode. The Quartus II software timing analyzer reports any phase difference between
the two. In normal mode, the PLL fully compensates the delay introduced by the
GCLK network.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1