EP3C5E144C8N Datasheet, PDF (335/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
2–21
Table 2–29. Cyclone III LS Devices True LVDS Transmitter Timing Specifications ⁽¹⁾
(Preliminary)
Symbol
Modes
C7 and I7
Min
Max
C8
Min
Max
×10
10
370
10
320
×8
10
370
10
320
f_HSCLK (input
×7
clock frequency)
×4
10
370
10
320
10
370
10
320
×2
10
370
10
320
×1
10
402.5
10
402.5
×10
100
740
100
640
×8
80
740
80
640
HSIODR
×7
70
740
70
640
×4
40
740
40
640
×2
20
740
20
640
×1
10
402.5
10
402.5
t_DUTY
TCCS
—
45
55
45
55
—
—
200
—
200
Output jitter
(peak to peak)
—
—
500
—
550
t_LOCK ⁽²⁾
—
—
1
—
1
Notes to Table 2–29:
(1) True LVDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6).
(2) t_LOCK is the time required for the PLL to lock from the end of device configuration.
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
ps
ps
ms
Table 2–30. Cyclone III LS Devices Emulated LVDS with Three-Resistor Network Transmitter
Timing Specifications ⁽¹⁾ (Part 1 of 2) (Preliminary)
Symbol
f_HSCLK (input
clock frequency)
HSIODR
t_DUTY
Modes
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
C7 and I7
Min
Max
10
320
10
320
10
320
10
320
10
320
10
402.5
100
640
80
640
70
640
40
640
20
640
10
402.5
45
55
C8
Min
Max
10
275
10
275
10
275
10
275
10
275
10
402.5
100
550
80
550
70
550
40
550
20
550
10
402.5
45
55
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 2