EP3C5E144C8N Datasheet, PDF (330/348 Pages) Altera Corporation – Ability to disable external JTAG port

2–16
Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
Table 2–20. Cyclone III LS Devices PLL Specifications ⁽⁴⁾ (Part 2 of 2) (Preliminary)
Symbol
Parameter
Min Typ Max
Unit
f_SCANCLK
scanclk frequency
— — 100
MHz
Notes to Table 2–20:
(1) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) With 100-MHz scanclk frequency.
(3) Peak-to-peak jitter with a probability level of 10^–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.
(4) V_{CCD_PLL} must be connected to V_CCINT through the decoupling capacitor and ferrite bead.
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less
than 200 ps.
(6) The V_CO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the V_CO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f_VCO specification.
Embedded Multiplier Specifications
Table 2–21 lists the embedded multiplier specifications for Cyclone III LS devices.
Table 2–21. Cyclone III LS Devices Embedded Multiplier Specifications (Preliminary)
Mode
Resources Used
EP3CLS70, EP3CLS100,
EP3CLS150, and EP3CLS200
Performance
Unit
Number of Multipliers
C7 and I7
C8
9 × 9-bit multiplier
1
300
260
MHz
18 × 18-bit multiplier
1
250
200
MHz
Memory Block Specifications
Table 2–22 lists the M9K memory block and logic element (LE) specifications for
Cyclone III LS devices.
Table 2–22. Cyclone III LS Devices Memory Block Performance Specifications (Preliminary)
Memory
Mode
EP3CLS70, EP3CLS100,
Resources Used
EP3CLS150, and EP3CLS200
Performance
Unit
LEs
M9K
Memory
C7 and I7
C8
FIFO 256 × 36
47
1
274
Single-port 256 × 36
0
1
274
M9K Block
Simple dual-port 256 × 36 CLK
0
1
274
True dual port 512 × 18 single CLK 0
1
274
238
MHz
238
MHz
238
MHz
238
MHz
Cyclone III Device Handbook
Volume 2
December 2011 Altera Corporation