EP3C5E144C8N Datasheet, PDF (216/348 Pages) Altera Corporation – Ability to disable external JTAG port

9–58
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Programming Serial Configuration Devices In-System Using the JTAG
Interface
Cyclone III device family in a single-device or in a multiple-device chain supports
in-system programming of a serial configuration device with the JTAG interface using
the SFL design. The intelligent host or download cable of the board can use the four
JTAG pins on the Cyclone III device family to program the serial configuration device
in system, even if the host or download cable cannot access the configuration pins
(DCLK, DATA, ASDI, and nCS pins).
The SFL design is a JTAG-based in-system programming solution for Altera serial
configuration devices. The SFL is a bridge design for the Cyclone III device family
that uses its JTAG interface to access the EPCS JTAG Indirect Configuration Device
Programming (.jic) file and then uses the AS interface to program the EPCS device.
Both the JTAG interface and AS interface are bridged together inside the SFL design.
In a multiple device chain, you must only configure the master device that controls
the serial configuration device. When using this feature, the slave devices in the
multiple device chain which are configured by the serial configuration device do not
need to be configured. To use this feature successfully, set the MSEL[3..0]pins of the
master device to select the AS configuration scheme (Table 9–7 on page 9–11). The
serial configuration device in-system programming through the Cyclone III device
family JTAG interface has three stages, which are described in the following sections:
■ “Loading the SFL Design” on page 9–58
■ “ISP of the Configuration Device” on page 9–59
■ “Reconfiguration” on page 9–60
Loading the SFL Design
The SFL design is a design inside the Cyclone III device family that bridges the JTAG
interface and the AS interface with glue logic.
The intelligent host uses the JTAG interface to configure the master device with a SFL
design. The SFL design allows the master device to control the access of four serial
configuration device pins, also known as the Active Serial Memory Interface (ASMI)
pins, through the JTAG interface. The ASMI pins are serial clock input (DCLK), serial
data output (DATA), AS data input (ASDI), and active-low chip select (nCS) pins.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation