EP3C5E144C8N Datasheet, PDF (333/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
2–19
Table 2–27. Cyclone III LS Devices Emulated RSDS with One-Resistor Network Transmitter Timing
Specifications ⁽¹⁾ (Preliminary)
Symbol
Modes
C7 and I7
C8
Unit
Min Typ Max Min Typ Max
×10
10
—
85
10 — 85
MHz
×8
f_HSCLK (input
×7
clock
frequency)
×4
×2
10
—
85
10 — 85
MHz
10
—
85
10 — 85
MHz
10
—
85
10 — 85
MHz
10
—
85
10 — 85
MHz
×1
10
— 170 10 — 170
MHz
×10
100 — 170 100 — 170 Mbps
×8
Device
×7
operation in
Mbps
×4
×2
80
— 170 80 — 170 Mbps
70
— 170 70 — 170 Mbps
40
— 170 40 — 170 Mbps
20
— 170 20 — 170 Mbps
×1
10
— 170 10 — 170 Mbps
t_DUTY
TCCS
—
45
—
55
45 — 55
%
—
—
— 200 — — 200
ps
Output jitter
(peak to
—
peak)
—
— 500 — — 550
ps
20 – 80%,
t_RISE
C_LOAD = 5 pF
— 500 —
— 500 —
ps
t_FALL
t_LOCK ⁽²⁾
20 – 80%,
C_LOAD = 5 pF
—
— 500 —
— 500 —
ps
—
—
1
——
1
ms
Notes to Table 2–27:
(1) Emulated RSDS with one-resistor network transmitter is supported at the output pin of all I/O banks.
(2) t_LOCK is the time required for the PLL to lock from the end of device configuration.
Table 2–28. Cyclone III LS Devices Mini-LVDS Transmitter Timing Specification ^{(1), (2)} (Part 1 of 2) (Preliminary)
Symbol
f_HSCLK (input
clock frequency)
Modes
×10
×8
×7
×4
×2
×1
C7 and I7
C8
Unit
Min
Typ Max
Min
Typ
Max
10
— 155.5
10
—
155.5
MHz
10
— 155.5
10
—
155.5
MHz
10
— 155.5
10
—
155.5
MHz
10
— 155.5
10
—
155.5
MHz
10
— 155.5
10
—
155.5
MHz
10
—
311
10
—
311
MHz
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 2