EP3C5E144C8N Datasheet, PDF (327/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 2: Cyclone III LS Device Data Sheet
Electrical Characteristics
2–13
Table 2–18. Differential I/O Standard Specifications ⁽¹⁾ (Part 2 of 2)
I/O
Standard
V_CCIO (V)
V_ID (mV)
Min Typ Max Min Max Min
V_ICM (V)
Condition
V_OD (mV) ⁽²⁾
Max Min Typ Max
V_OS (V) ⁽²⁾
Min Typ Max
LVDS
(Column
I/Os)
2.375
BLVDS
(Row
I/Os) ⁽⁴⁾
2.375
BLVDS
(Column
I/Os) ⁽⁴⁾
2.375
mini-LVDS
(Row
2.375
I/Os) ⁽⁵⁾
mini-LVDS
(Column 2.375
I/Os) ⁽⁵⁾
RSDS
(Row
I/Os) ⁽⁵⁾
2.375
RSDS
(Column
I/Os) ⁽⁵⁾
2.375
PPDS
(Row
I/Os) ⁽⁵⁾
2.375
PPDS
(Column
I/Os) ⁽⁵⁾
2.375
2.5 2.625 100 —
2.5 2.625 100 —
2.5 2.625 100 —
2.5 2.625 — —
2.5 2.625 — —
2.5 2.625 — —
2.5 2.625 — —
2.5 2.625 — —
2.5 2.625 — —
0 D_MAX ≤ 500 Mbps
0.5
500 Mbps ≤ D_MAX
≤ 700 Mbps
1 D_MAX > 700 Mbps
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.85
1.85 247 — 600 1.125 1.25 1.35
1.6
— —— — — — —
— —— — — — —
— 300 — 600 1.0 1.2 1.4
— 300 — 600 1.0 1.2 1.4
— 100 200 600 0.5 1.2 1.5
— 100 200 600 0.5 1.2 1.5
— 100 200 600 0.5 1.2 1.4
— 100 200 600 0.5 1.2 1.4
Notes to Table 2–18:
(1) For an explanation of the terms used in Table 2–18, refer to “Transmitter Output Waveform” in “Glossary” on page 2–26.
(2) R_L range: 90 ≤ R_L ≤ 110 Ω .
(3) The LVPECL input standard is only supported at clock input. The output standard is not supported.
(4) There is no fixed V_ICM, V_OD, and V_OS specification for BLVDS. They are dependent on the system topology.
(5) Mini-LVDS, RSDS, and PPDS standards are only supported at output pins of Cyclone III LS devices.
Power Consumption
Use the following methods to estimate power for your design:
■ The Excel-based EPE
■ The Quartus II^® PowerPlay power analyzer feature
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 2