EP3C5E144C8N Datasheet, PDF (211/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–53
When programming a JTAG device chain, one JTAG-compatible header is connected
to several devices. The number of devices in the JTAG chain is limited only by the
drive capability of the download cable. When four or more devices are connected in a
JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an on-board
buffer.
JTAG-chain device programming is ideal when the system contains multiple devices,
or when testing your system using JTAG BST circuitry. Figure 9–26 and Figure 9–27
show a multi-device JTAG configuration.
For the device V_CCIO of 2.5, 3.0, and 3.3 V, refer to Figure 9–26. All I/O inputs must
maintain a maximum AC voltage of 4.1 V. Because JTAG pins do not have the internal
PCI clamping diodes to prevent voltage overshoot when using V_CCIO of 2.5, 3.0, and
3.3 V, you must power up the V_CC of the download cable with a 2.5-V supply from
V_CCA.
For device V_CCIO of 1.2, 1.5, and 1.8 V, refer to Figure 9–27. You can power up the V_CC
of the download cable with the supply from V_CCIO.
Figure 9–26. JTAG Configuration of Multiple Devices Using a Download Cable (2.5, 3.0, and 3.3-V V_CCIO Powering the
JTAG Pins)
Download Cable
10-Pin Male Header
Pin 1
VCCA
(6)
VCCA (5) _VCCA
(6)
VIO
(3)
VCCIO (1)
Cyclone III Device
10 kΩ
Family
VCCIO(1)
10 kΩ
nSTATUS
(2)
DATA[0]
(2) DCLK
(2)
nCONFIG
(2)
MSEL[3..0] CONF_DONE
(2)
nCEO
nCE (4)
VCCIO(1)
Cyclone III Device
10 kΩ
Family
VCCIO(1)
10 kΩ
VCCIO ⁽¹⁾
10 kΩ
Cyclone III Device
Family
VCCIO ⁽¹⁾
10 kΩ
nSTATUS
(2)
DATA[0]
(2) DCLK
(2)
nCONFIG
(2)
MSEL[3..0] CONF_DONE
(2)
nCEO
nCE (4)
nSTATUS
(2)
DATA[0]
(2) DCLK
(2)
nCONFIG
(2)
MSEL[3..0] CONF_DONE
(2)
nCEO
nCE (4)
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
1 kΩ
Notes to Figure 9–26:
(1) Connect these pull-up resistors to the V_CCIO supply of the bank in which the pin resides.
(2) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect the
nCONFIG pin to logic high and the MSEL[3..0] pins to ground. In addition, pull DCLK and DATA[0] either high or low, whichever is convenient
on your board.
(3) Pin 6 of the header is a V_IO reference voltage for the MasterBlaster output driver. V_IO must match the V_CCA of the device. For this value, refer to the
MasterBlaster Serial/USB Communications Cable User Guide. In the ByteBlasterMV cable, this pin is a no connect. In the USB-Blaster and
ByteBlaster II cables, this pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.
(4) The nCE pin must be connected to ground or driven low for successful JTAG configuration.
(5) Power up the V_CC of the ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5- V supply from V_CCA. Third-party programmers must switch
to 2.5 V. Pin 4 of the header is a V_CC power supply for the MasterBlaster cable. The MasterBlaster cable can receive power from either 5.0- or 3.3-V
circuit boards, DC power supply, or 5.0 V from the USB cable. For this value, refer to the MasterBlaster Serial/USB Communications User Guide.
(6) The resistor value can vary from 1 kΩ to 10 kΩ. Perform signal integrity analysis to select the resistor value for your setup.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1