EP3C5E144C8N Datasheet, PDF (177/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–19
Single SRAM Object File
The second method configures both the master device and slave devices with the
same .sof. The serial configuration device stores one copy of the .sof. This setup is
shown in Figure 9–6 where the master is set up in AS mode and the slave devices are
set up in PS mode. You must set up one or more slave devices in the chain. All the
slave devices must be set up as shown in Figure 9–6.
Figure 9–6. Multi-Device AS Configuration where the Devices Receive the Same Data with a Single .sof
V_CCIO (1) V_CCIO (1) V_CCIO (1)
10 kΩ
10 kΩ
10 kΩ
Serial Configuration
Device
Master Device of the Cyclone III
Device Family
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
N.C. (2)
Slave Device 1 of the Cyclone III
Device Family
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
N.C. (2)
Slave Device 2 of the Cyclone III
Device Family
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
N.C. (2)
DATA
DCLK
nCS
ASDI
25 Ω (5)
50 Ω (5),(7)
DATA[0]
DCLK
nCSO (4)
ASDO (4)
MSEL[3..0] (3)
DATA[0]
DCLK
MSEL[3..0] (3)
DATA[0]
DCLK
MSEL[3..0] (3)
50 Ω(7)
Buffers (6)
Notes to Figure 9–6:
(1) Connect the pull-up resistors to the V_CCIO supply of the bank in which the pin resides.
(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device of the Cyclone III device
family in AS mode and the slave devices in PS mode. To connect MSEL[3..0] for the master device in AS mode and slave devices in PS mode,
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to V_CCA or GND.
(4) These are dual-purpose I/O pins. The nCSO pin functions as the FLASH_NCE pin in AP mode. The ASDO pin functions as the DATA[1] pin in other
AP and FPP modes.
(5) Connect the series resistor at the near end of the serial configuration device.
(6) Connect the repeater buffers between the master and slave devices for DATA[0] and DCLK. All I/O inputs must maintain a maximum AC voltage
of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in “Configuration and JTAG Pin I/O
Requirements” on page 9–7.
(7) The 50-Ω series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50-Ω series
resistors if the 2.5- or 3.0-V configuration voltage standard is applied.
In this setup, all the Cyclone III device family in the chain are connected for
concurrent configuration. This can reduce the AS configuration time because all the
Cyclone III device family is configured in one configuration cycle. Connect the nCE
input pins of all the Cyclone III device family to ground. You can either leave the nCEO
output pins on all the Cyclone III device family unconnected or use the nCEO output
pins as normal user I/O pins. The DATA and DCLK pins are connected in parallel to all
the Cyclone III device family.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1