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EP3C5E144C8N Datasheet, PDF (145/348 Pages) Altera Corporation – Ability to disable external JTAG port | |||
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Chapter 8: External Memory Interfaces in the Cyclone III Device Family
8â3
Cyclone III Device Family Memory Interfaces Pin Support
1 Cyclone III device family does not support differential strobe pins, which is an
optional feature in the DDR2 SDRAM device.
f When you use the Altera Memory Controller MegaCore®, the PHY is instantiated for
you. For more information about the memory interface data path, refer to the External
Memory Interfaces page.
1 ALTMEMPHY is a self-calibrating megafunction, enhanced to simplify the
implementation of the read-data path in different memory interfaces. The
auto-calibration feature of ALTMEMPHY provides ease-of-use by optimizing clock
phases and frequencies across process, voltage, and temperature (PVT) variations.
You can save on the global clock resources in Cyclone III device family through the
ALTMEMPHY megafunction because you are not required to route the DQS signals on
the global clock buses (because DQS is ignored for read capture). Resynchronization
issues do not arise because no transfer occurs from the memory domain clock (DQS) to
the system domain for capturing data DQ.
All I/O banks in Cyclone III device family can support DQ and DQS signals with DQ-bus
modes of Ã8, Ã9, Ã16, Ã18, Ã32, and Ã36. DDR2 and DDR SDRAM interfaces use Ã8
mode DQS group regardless of the interface width. For wider interface, you can use
multiple Ã8 DQ groups to achieve the desired width requirement.
In the Ã9, Ã18, and Ã36 modes, a pair of complementary DQS pins (CQ and CQ#)
drives up to 9, 18, or 36 DQ pins, respectively, in the group, to support one, two, or four
parity bits and the corresponding data bits. The Ã9, Ã18, and Ã36 modes support the
QDR II memory interface. CQ# is the inverted read-clock signal which is connected to
the complementary data strobe (DQS or CQ#) pin. You can use any unused DQ pins as
regular user I/O pins if they are not used as memory interface signals.
Table 8â1 lists the number of DQS or DQ groups supported on each side of the
Cyclone III device only.
Table 8â1. Cyclone III Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 1 of 4)
Device
EP3C5
Package
144-pin EQFP (1)
164-pin MBGA (1)
256-pin FineLine
BGA/256-pin
Ultra FineLine
BGA (1)
Side
Left
Right
Top (2)
Bottom (3), (4)
Left
Right
Top (2)
Bottom (3), (4)
Left (4), (5)
Right (4), (6)
Top
Bottom
Number
Ã8
Groups
0
0
1
1
0
0
1
1
1
1
2
2
Number
Ã9
Groups
0
0
0
0
0
0
0
0
1
1
2
2
Number
Ã16
Groups
0
0
0
0
0
0
0
0
0
0
1
1
Number
Ã18
Groups
0
0
0
0
0
0
0
0
0
0
1
1
Number
Ã32
Groups
â
â
â
â
â
â
â
â
â
â
â
â
Number
Ã36
Groups
â
â
â
â
â
â
â
â
â
â
â
â
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
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