EP3C5E144C8N Datasheet, PDF (324/348 Pages) Altera Corporation – Ability to disable external JTAG port

2–10
Chapter 2: Cyclone III LS Device Data Sheet
Electrical Characteristics
Schmitt Trigger Input
Cyclone III LS devices support Schmitt trigger input on TDI, TMS, TCK, nSTATUS,
nCONFIG, nCE, CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces
hysteresis to the input signal for improved noise immunity, especially for signals with
a slow edge rate. Table 2–12 lists the hysteresis specifications across supported V_CCIO
range for Schmitt trigger inputs in Cyclone III LS devices.
Table 2–12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III LS Devices
Symbol
Parameter
V_SCHMITT
Hysteresis for Schmitt trigger
input
Conditions
V_CCIO = 3.3 V
V_CCIO = 2.5 V
V_CCIO = 1.8 V
V_CCIO = 1.5 V
Minimum
200
200
140
110
Typical
—
—
—
—
Maximum Unit
—
mV
—
mV
—
mV
—
mV
I/O Standard Specifications
The following tables list input voltage sensitivities (V_IH and V_IL), output voltage
(V_OH and V_OL), and current drive characteristics (I_OH and I_OL) for various I/O
standards supported by Cyclone III LS devices.
Table 2–13 through Table 2–18 provide Cyclone III LS devices I/O standard
specifications.
Table 2–13. Cyclone III LS Devices Single-Ended I/O Standard Specifications ⁽¹⁾
I/O Standard
V_CCIO (V)
Min Typ Max
V_IL (V)
Min Max
V_IH (V)
Min
Max
V_OL (V)
Max
V_OH (V)
Min
3.3-V LVTTL ⁽²⁾ 3.135 3.3 3.465 — 0.8 1.7
3.6
0.45
2.4
3.3-V LVCMOS ⁽²⁾ 3.135 3.3 3.465 — 0.8 1.7
3.6
0.2
V_CCIO – 0.2
3.0-V LVTTL ⁽²⁾
2.85 3.0 3.15 –0.3 0.8 1.7 V_CCIO + 0.3 0.45
2.4
3.0-V LVCMOS ⁽²⁾ 2.85 3.0 3.15 –0.3 0.8 1.7 V_CCIO + 0.3
0.2
V_CCIO – 0.2
2.5-V LVTTL and
LVCMOS ⁽²⁾
2.375 2.5 2.625 –0.3
0.7
1.7
3.6
0.4
2.0
1.8-V LVTTL and
LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
PCI
PCI-X
1.71
1.8
1.89
–0.3
0.35 *
V_CCIO
0.65 *
V_CCIO
2.25
0.45
V_CCIO –
0.45
1.425
1.5
1.575
–0.3
0.35 *
V_CCIO
0.65 *
V_CCIO
V_CCIO + 0.3
0.25 *
V_CCIO
0.75 *
V_CCIO
1.14
1.2
1.26
–0.3
0.35 *
V_CCIO
0.65 *
V_CCIO
V_CCIO + 0.3
0.25 *
V_CCIO
0.75 *
V_CCIO
2.85
3.0
3.15
—
0.30*
V_CCIO
0.50*
V_CCIO
V_CCIO + 0.3 0.1 * V_CCIO
0.9 * V_CCIO
2.85
3.0
3.15
—
0.35*
V_CCIO
0.50*
V_CCIO
V_CCIO + 0.3 0.1 * V_CCIO
0.9 * V_CCIO
Notes to Table 2–13:
(1) AC load CL = 10 pF.
(2) For more information about interfacing Cyclone III LS devices with 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS I/O standards,
refer to AN 447: Interfacing Cyclone III and Cyclone iV Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O Systems.
I_OL
(mA)
4
2
4
0.1
1
2
2
2
1.5
1.5
I_OH
(mA)
–4
–2
–4
–0.1
–1
–2
–2
–2
–0.5
–0.5
Cyclone III Device Handbook
Volume 2
December 2011 Altera Corporation