EP3C5E144C8N Datasheet, PDF (336/348 Pages) Altera Corporation – Ability to disable external JTAG port

2–22
Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
Table 2–30. Cyclone III LS Devices Emulated LVDS with Three-Resistor Network Transmitter
Timing Specifications ⁽¹⁾ (Part 2 of 2) (Preliminary)
Symbol
Modes
C7 and I7
Min
Max
C8
Unit
Min
Max
TCCS
—
—
200
—
200
ps
Output jitter
(peak to peak)
—
—
500
—
550
ps
t_LOCK ⁽²⁾
—
—
1
—
1
ms
Notes to Table 2–30:
(1) Emulated LVDS with three-resistor network transmitter is supported at the output pin of all I/O banks.
(2) t_LOCK is the time required for the PLL to lock from the end of device configuration.
Table 2–31. Cyclone III LS Devices LVDS Receiver Timing Specifications ⁽¹⁾
(Preliminary)
Symbol
Modes
C7 and I7
Min
Max
C8
Min
Max
×10
10
370
10
320
×8
10
370
10
320
f_HSCLK (input
×7
clock frequency)
×4
10
370
10
320
10
370
10
320
×2
10
370
10
320
×1
10
402.5
10
402.5
×10
100
740
100
640
×8
80
740
80
640
HSIODR
×7
70
740
70
640
×4
40
740
40
640
×2
20
740
20
640
×1
10
402.5
10
402.5
SW
—
—
400
—
400
Input jitter
tolerance
—
—
500
—
550
t_LOCK ⁽²⁾
—
—
1
—
1
Notes to Table 2–31:
(1) True LVDS receiver is supported at all banks.
(2) t_LOCK is the time required for the PLL to lock from the end of device configuration.
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
ps
ps
External Memory Interface Specifications
Cyclone III LS devices support external memory interfaces up to 200 MHz. The
external memory interfaces for Cyclone III LS devices are auto-calibrating and easy to
implement.
Table 2–32 and Table 2–33 list the external memory interface specifications for
Cyclone III LS devices and are useful when performing memory interface timing
analysis.
Cyclone III Device Handbook
Volume 2
December 2011 Altera Corporation