EP3C5E144C8N Datasheet, PDF (155/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Features
8–13
f For more information about Cyclone III device family IOE registers, refer to the
I/O Features in the Cyclone III Device Family chapter.
Figure 8–6 shows how the second output enable register extends the DQS
high-impedance state by half a clock cycle during a write operation.
Figure 8–6. Extending the OE Disable by Half a Clock Cycle for a Write Transaction ⁽¹⁾
System clock
(outclock for DQS)
OE for DQS
(from logic array)
90^o
DQS
Write Clock
(outclock for DQ,
-90^ophase shifted
from System Clock)
datain_h
(from logic array)
datain_I
(from logic array)
OE for DQ
(from logic array)
DQ
Delay
by Half
a Clock
Cycle
Preamble
Postamble
D0
D2
D1
D3
D0
D1
D2
D3
Note to Figure 8–6:
(1) The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the Quartus II software implements
the signal as an active high and automatically adds an inverter before the A_OE register D input.
OCT
Cyclone III device family supports calibrated on-chip series termination (R_S OCT) in
both vertical and horizontal I/O banks. To use the calibrated OCT, you must use the
RUP and RDN pins for each R_S OCT control block (one for each side). You can use
each OCT calibration block to calibrate one type of termination with the same V_CCIO
for that given side.
f For more information about Cyclone III device family OCT calibration block, refer to
the Cyclone III Device I/O Features chapter.
PLL
When interfacing with external memory, the PLL is used to generate the memory
system clock, the write clock, the capture clock and the logic-core clock. The system
clock generates the DQS write signals, commands, and addresses. The write-clock is
shifted by -90° from the system clock and generates the DQ signals during writes. You
can use the PLL reconfiguration feature to calibrate the read-capture phase shift to
balance the setup and hold margins.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1