EP3C5E144C8N Datasheet, PDF (318/348 Pages) Altera Corporation – Ability to disable external JTAG port

2–4
Chapter 2: Cyclone III LS Device Data Sheet
Electrical Characteristics
Recommended Operating Conditions
This section lists the functional operation limits for AC and DC parameters for
Cyclone III LS devices.
The steady-state voltage and current values expected from Cyclone III LS devices are
provided in Table 2–3. All supplies must be strictly monotonic without plateaus.
Table 2–3. Cyclone III LS Devices Recommended Operating Conditions ^{(1), (2)}
Symbol
V_CCINT ⁽³⁾
V_CCIO ^{(3), (7)}
V_CCA ⁽³⁾
V_{CCD_PLL} ⁽³⁾
V_CCBAT ⁽⁴⁾
V_I
V_O
T_J
Parameter
Supply voltage for internal logic
Supply voltage for output buffers, 3.3-V
operation
Supply voltage for output buffers, 3.0-V
operation
Supply voltage for output buffers, 2.5-V
operation
Supply voltage for output buffers, 1.8-V
operation
Supply voltage for output buffers, 1.5-V
operation
Supply voltage for output buffers, 1.2-V
operation
Supply (analog) voltage for PLL regulator
Supply (digital) voltage for PLL
Battery back-up power supply for design
security volatile key register
Input voltage
Output voltage
Operating junction temperature
t_RAMP
I_Diode
Power supply ramptime
Magnitude of DC current across
PCI-clamp diode when enabled
Conditions
—
—
—
—
—
—
—
—
—
—
—
—
For commercial use
For industrial use
Standard POR ⁽⁵⁾
Fast POR ⁽⁶⁾
—
Min Typ Max Unit
1.15 1.2 1.25 V
3.135 3.3 3.465 V
2.85 3.0 3.15 V
2.375 2.5 2.625 V
1.71 1.8 1.89 V
1.425 1.5 1.575 V
1.14 1.2 1.26 V
2.375 2.5 2.625 V
1.15 1.2 1.25 V
1.2
3.0
3.3
V
–0.5 —
3.6
V
0
—
V_CCIO
V
0
—
85
°C
–40
—
100 °C
50 µs — 50 ms —
50 µs — 3 ms —
—
—
10 mA
Notes to Table 2–3:
(1) V_CCIO for all I/O banks must be powered up during device operation. All V_CCA pins must be powered to 2.5 V (even when you do not use phase
locked-loops [PLLs}), and must be powered up and powered down at the same time.
(2) V_{CCD_PLL} must always be connected to V_CCINT through a decoupling capacitor and ferrite bead.
(3) V_CC must rise monotonically.
(4) V_CCBAT is tied to POR. If the V_CCBAT is below 1.2 V, the device will not power up.
(5) POR time for Standard POR ranges from 50 to 200 ms. Each individual power supply must reach the recommended operating range within
50 ms.
(6) POR time for Fast POR ranges from 3 to 9 ms. Each individual power supply must reach the recommended operating range within 3 ms.
(7) All input buffers are powered by the V_CCIO supply.
DC Characteristics
This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT)
tolerance, and bus hold specifications for Cyclone III LS devices.
Cyclone III Device Handbook
Volume 2
December 2011 Altera Corporation