EP3C5E144C8N Datasheet, PDF (334/348 Pages) Altera Corporation – Ability to disable external JTAG port

2–20
Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
Table 2–28. Cyclone III LS Devices Mini-LVDS Transmitter Timing Specification ^{(1), (2)} (Part 2 of 2) (Preliminary)
Symbol
Modes
C7 and I7
C8
Unit
Min
Typ Max
Min
Typ
Max
×10
100
—
311
100
—
311
Mbps
×8
80
—
311
80
—
311
Mbps
Device operation
×7
in Mbps
×4
70
—
311
70
40
—
311
40
—
311
—
311
Mbps
Mbps
×2
20
—
311
20
—
311
Mbps
×1
10
—
311
10
—
311
Mbps
t_DUTY
TCCS
—
45
—
55
45
—
55
%
—
—
—
200
—
—
200
ps
Output jitter
(peak to peak)
—
—
—
500
—
—
550
ps
20 – 80%,
t_RISE
C_LOAD = 5 pF
—
500
—
—
500
—
ps
t_FALL
t_LOCK ⁽³⁾
20 – 80%,
C_LOAD = 5 pF
—
—
500
—
—
500
—
ps
—
—
1
—
—
1
ms
Notes to Table 2–28:
(1) Applicable for true and emulated mini-LVDS with three-resistor network transmitter.
(2) True mini-LVDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS with three-resistor
network transmitter is supported at the output pin of all I/O banks.
(3) t_LOCK is the time required for the PLL to lock from the end of device configuration.
Cyclone III Device Handbook
Volume 2
December 2011 Altera Corporation