EP3C5E144C8N Datasheet, PDF (343/348 Pages) Altera Corporation – Ability to disable external JTAG port

Chapter 2: Cyclone III LS Device Data Sheet
Glossary
2–29
Table 2–39. Glossary (Part 4 of 6)
Letter
Term
Definitions
V_CCIO
VOH
V_REF
VIH (AC )
VIH(DC)
VIL (D C)
VIL (AC )
Single-ended
Voltage
referenced I/O
S ^Standard
VOL
V_SS
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values.
■ The AC values indicate the voltage levels at which the receiver must meet its timing
specifications.
■ The DC values indicate the voltage levels at which the final logic state of the receiver is
unambiguously defined.
After the receiver input crosses the AC value, the receiver changes to the new logic state. The
new logic state is then maintained as long as the input stays beyond the DC threshold. This
approach is intended to provide predictable receiver timing in the presence of input waveform
ringing.
SW (Sampling
Window)
High-speed I/O Block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling
window.
t_C
TCCS (Channel-
to-channel-skew)
tcin
High-speed receiver and transmitter input and output clock period.
High-speed I/O Block: The timing difference between the fastest and slowest output edges,
including t_CO variation and clock skew. The clock is included in the TCCS measurement.
Delay from the clock pad to the I/O input register.
t_CO
tcout
Delay from the clock pad to the I/O output.
Delay from the clock pad to the I/O output register.
t_DUTY
High-speed I/O Block: Duty cycle on the high-speed transmitter output clock.
T
t_FALL
t_H
Signal high-to-low transition time (80 to 20%).
Input register hold time.
Timing Unit
High-speed I/O block: The timing budget allowed for skew, propagation delays, and the data
Interval (TUI)
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w).
t_INJITTER
Period jitter on the PLL clock input.
t_{OUTJITTER_DEDCLK} Period jitter on the dedicated clock output driven by a PLL.
t_{OUTJITTER_IO}
Period jitter on the general purpose I/O driven by a PLL.
tpllcin
Delay from the PLL inclk pad to the I/O input register.
tpllcout
Delay from the PLL inclk pad to the I/O output register.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 2